The demand for digital communications over the Internet has resulted in protocols capable of supporting large bandwidths of data to the consumer. For example, cable and Asynchronous Digital Subscriber Loop (ADSL) modems have the ability to supply data at a rate in upwards of 8 Mbps (Megabits/second). However, the ability to meet these data rates is often limited by the delay and other capabilities of individual systems and their components.
For example, low power systems may be limited by the amount of power dissipation associated with receiving data at such a high rate, while a high performance system may be limited by the sampling rate of its analog components. One a system component which often limits the ability of a system to reach its maximum performance is a receiver front end. A receiver front end is the analog circuitry that converts an analog signal to digital data. Where Complementary Metal Oxide Semiconductor (CMOS) technology is used to implement a receiver front end, the sampling rates of the prior art can limit performance of the receiver front end, and at high data rates the power dissipation is often unacceptable.
Therefore, an A-D converter capable of improving the bandwidth and reducing power dissipation in high-performance communication devices would be useful.